1. Field of the Invention
The present invention relates to a power charge pump for low supply voltage applications, which is able to supply high DC output currents.
2. Description of the Related Art
Pumps of the above type find a typical application in nonvolatile memories, such as EPROM and flash memories, wherein parallel writing of the cells is envisaged, parallel writing requiring output currents of the order of tenths of mA to meet the ever more demanding speed requirements.
In particular, for this type of memories, it is often required to supply internally the writing voltage of 4.5 V, to be applied to the drain terminals of the cells, without having to supply it from outside. A further requirement is to avoid the use of large capacitive structures outside the auxiliary chip or chips, such as a DC/DC converter.
The basic diagram of a generic known charge pump is shown in FIG. 1, wherein a charge pump 1 is formed by a first and a second branch 2s, 2d, parallel to one another and including a single stage, and by a phase-generating stage 7.
The two branches 2s, 2d have the same structure. In addition, the phase-generating stage 7 is formed by two symmetrical parts which supply phase signals xcfx86 and xcfx86N for the first and for the second branch 2s, 2d. Consequently, the corresponding components are designated by the same reference numbers and by a letter s or d according to whether they refer to the first branch 2s or to the second branch 2d. 
In detail, each branch 2s, 2d comprises a first switch and a second switch which are connected at an intermediate node 5s, resp. 5d, and are implemented by a charging transistor 3s, resp. 3d, and a charge-transfer transistor of NMOS type 4s, resp. 4d. In particular, the drain terminals of the charging transistors 3s, 3d are connected to a supply line 10 feeding a supply voltage VDD. The source terminal of the charging transistor 3s, resp. 3d, is connected to the intermediate node 5s, resp. 5d, and the gate terminal of the charging transistor 3s, resp. 3d, receives a respective control signal V1s, V1d. In addition, the drain terminal of the charge-transfer transistor 4s, resp. 4d, is connected to the intermediate node 5s, resp. 5d. In addition, the drain terminal of the charge-transfer transistor 4s, resp. 4d, is connected to the intermediate node 5s, resp. 5d. Both source terminals of the charge-transfer transistors 4s, 4d are connected to an output node 11, and the gate terminal of the charge-transfer transistor 4s, resp. 4d, receives a respective control signal V2s, V2d. 
Each branch 2s, 2d further comprises a boosting capacitor 12s, resp. 12d, which has a first terminal connected to the intermediate node 5s, resp. 5d, and a second terminal connected to an output 14s, resp. 14d, of a first 13s, resp. a second inverter 13d. 
The inverters 13s, resp. 13d, belong to the phase-generating stage 7 and each comprise a PMOS transistor 19s, resp. 19d, and an NMOS transistor 20s, resp. 20d, connected together in series between the supply line 10 and the ground line 15. The inverters 13s, resp. 13d, have a respective input 16s, 16d which receives a respective oscillating signal F, FN, generated by an oscillator 18. The oscillating signals F, FN are in phase opposition and oscillate between the supply voltage VDD and 0 V. Phase signals xcfx86 and xcfx86N, in phase opposition to each other, are thus present on the outputs 14s, resp. 14d. 
Boosted voltages Vs, resp. Vd are present on the intermediate nodes 5s, 5d; the output node 11, at an output voltage Vout, supplies a current Iout.
Operation of the charge pump 1 will now be described with reference to the first branch 2s; the second branch 2d behaves in the same way, but is out of phase by T/2, where T is the period of the oscillator 18.
When the oscillating signal F coming from the oscillator 18 switches to the high state (VDD), the output 14s of the first inverter 13s is at 0 V, and the boosting capacitor 12s charges up to the supply voltage VDD through the charging transistor 3s, which is on. When the oscillating signal F switches to 0 V, the output 14s of the first inverter 13s is high (VDD), the charging transistor 3s is off, and the voltage Vs tends to go to 2VDD. In addition, the charge-transfer transistor 4s is on and transfers the boosted voltage Vs to the output 11.
The operation described above is, however, correct only when the charge pump is not required to supply DC current at output. In fact, the maximum output voltage of the charge pump 1 is different according to whether a capacitive load or an ideal DC generator is connected to the output 11. In fact, in case of a capacitive load, the charge pump 1 must supply current only in the charging transient of the output capacitor, and subsequently must only supply a minimal current in order to compensate any losses. In this case, the current that can be supplied by the charge pump 1 affects only the rapidity of the transient, but does not affect the voltage Vout that may be obtained at output under steady-state conditions. This situation typically occurs when the charge pump 1 is used for driving in parallel the gate terminals of memory cells.
If, instead, the load requires DC current, as when the drain terminals of the memory cells are to be biased during writing, it is necessary to consider the voltage drops xcex94VMP, xcex94VC and xcex94VM4 across the PMOS transistors 19s, 19d, the boosting capacitors 12s, 12d, and the charge-transfer transistors 4s, 4d, and are due to passage of current in these components.
The output voltage Vout alternately follows the trend of the boosted voltages Vs, Vd minus the drops across the charge-transfer transistors 4s, 4d. The obtainable overall waveform of the output voltage Vout, considering the voltage drops mentioned, is illustrated in FIG. 2, which shows both the reduction in the maximum value due to the voltage drops xcex94VMP and xcex94VM4 and the ripple that is due to the boosting capacitors 12s, 12d, the value of which depends upon the sizing of the boosting capacitors 12s, 12d. 
In particular, hereinafter the impact of the circuit parameters and characteristics of the charge pump 1 on the voltage drops xcex94VMP, xcex94VC and xcex94VM4 is evaluated. Also in this case, reference will be made to the PMOS transistor 19s, the charge-transfer transistor 4s and the boosting capacitor 12s of the first branch, and the ensuing description also applies to the second branch 2d. 
Calculation of xcex94VMP 
When the oscillating signal F is low (0 V), the PMOS transistor 19s is on. On the assumption that across the PMOS transistor 19s there is a voltage drop xcex94VMP having a low value, the PMOS transistor 19s works in the ohmic region. Consequently, the current Iout that flows in the PMOS transistor 19s, and then in the boosting capacitor 12s, in the charge-transfer transistor 4s and then to the output 11 can be expressed, to a first approximation, as       I    ⁢          xe2x80x83        ⁢    o    ⁢          xe2x80x83        ⁢    u    ⁢          xe2x80x83        ⁢    t    =            μ      P        ⁢                  W        P                    L        P              ⁢                  C                  o          ⁢                      xe2x80x83                    ⁢          x                    ⁡              (                                            V                              D                ⁢                                  xe2x80x83                                ⁢                D                                      -                    |                      V                          t              ⁢                              xe2x80x83                            ⁢              h              ⁢                              xe2x80x83                            ⁢              P                                |                )              ⁢    Δ    ⁢          xe2x80x83        ⁢          V              M        ⁢                  xe2x80x83                ⁢        P            
where xcexcP is the electronic mobility, Cox is the capacitance of the gate oxide, WP/LP is the aspect ratio, and VthP is the threshold voltage of the PMOS transistor 19s. We thus obtain       Δ    ⁢          xe2x80x83        ⁢          V              M        ⁢                  xe2x80x83                ⁢        P              =            I      ⁢              xe2x80x83            ⁢      o      ⁢              xe2x80x83            ⁢      u      ⁢              xe2x80x83            ⁢      t                      μ        P            ⁢                        W          P                          L          P                    ⁢                        C                      o            ⁢                          xe2x80x83                        ⁢            x                          ⁡                  (                                                    V                                  D                  ⁢                                      xe2x80x83                                    ⁢                  D                                            -                        |                          V                              t                ⁢                                  xe2x80x83                                ⁢                h                ⁢                                  xe2x80x83                                ⁢                P                                      |                    )                    
The electronic mobility and the capacitance of the oxide are preset process parameters. The designer can therefore act only on the sizing of the aspect ratio.
Calculation of xcex94VC 
The voltage drop xcex94VC on the boosting capacitor 12s is linked to the oscillation half-period xcex94T according to the following relation:       I    ⁢          xe2x80x83        ⁢    o    ⁢          xe2x80x83        ⁢    u    ⁢          xe2x80x83        ⁢    t    =            C      ⁢                        Δ          ⁢                      xe2x80x83                    ⁢                      V            C                                    Δ          ⁢                      xe2x80x83                    ⁢          T                      =          C      ⁢              xe2x80x83            ⁢      Δ      ⁢              xe2x80x83            ⁢              V        C            ⁢      2      ⁢              f                  o          ⁢                      xe2x80x83                    ⁢          s          ⁢                      xe2x80x83                    ⁢          c                    
wherein fosc=1/xcex94T is the oscillation frequency of the oscillator 18, and C is the capacitance of the boosting capacitor 12s. We thus have       Δ    ⁢          xe2x80x83        ⁢          V      C        =            I      ⁢              xe2x80x83            ⁢      o      ⁢              xe2x80x83            ⁢      u      ⁢              xe2x80x83            ⁢      t              2      ⁢              f                  o          ⁢                      xe2x80x83                    ⁢          s          ⁢                      xe2x80x83                    ⁢          c                    ⁢      C      
In order to reduce the above potential difference, it is possible to act only on the oscillation frequency fosc and on the capacitance C.
Calculation of xcex94VM4 
Analogously to what has been described for PMOS transistor 19a, the voltage on the charge-transfer transistor 4s is       Δ    ⁢          xe2x80x83        ⁢          V      M4        =            I      ⁢              xe2x80x83            ⁢      o      ⁢              xe2x80x83            ⁢      u      ⁢              xe2x80x83            ⁢      t                      μ        N            ⁢                        W          N                          L          N                    ⁢                        C                      o            ⁢                          xe2x80x83                        ⁢            x                          ⁡                  (                                    V                              2                ⁢                s                                      -                          V              ⁢                              xe2x80x83                            ⁢              o              ⁢                              xe2x80x83                            ⁢              u              ⁢                              xe2x80x83                            ⁢              t                        -                          V                              t                ⁢                                  xe2x80x83                                ⁢                h                ⁢                                  xe2x80x83                                ⁢                N                                              )                    
where xcexcN is the electronic mobility of N-type dopant, Cox is the capacitance of the gate oxide, WN/LN is the aspect ratio, and VthN is the threshold voltage of the charge-transfer transistor 4s. 
In this case, in addition to the possibility of acting on the aspect ratio, it is also possible to act on the voltage V2s applied to the gate terminal of the charge-transfer transistor 4s. 
In particular, if the charge-transfer transistors 4s, 4d (as for the charging transistors 3s, 3d) are driven by switches connecting their drain terminals with the respective gate terminals during conduction, and are thus diode-connected, they have a high voltage drop due to the body effect, with a consequent considerable reduction in the efficiency of the charge pump 1.
In order to eliminate the problem of the body effect, charge pumps are known, referred to as xe2x80x9ccross pumps,xe2x80x9d which use four different phases for driving the charging transistors 3s, 3d and the charge-transfer transistors 4s, 4d. A simplified diagram of a charge pump 28 of the xe2x80x9ccross pumpxe2x80x9d type is shown in FIG. 3 and will be briefly described hereinafter.
The charge pump 28 has a basic structure similar to that of the known charge pump of FIG. 1. The components in common with those of the known charge pump of FIG. 1 are therefore designated by the same reference numbers. In FIG. 3, however, the phase-generating stage is not shown, while the driving circuits are shown.
In particular, the charge pump 28 comprise a first and a second branch 2s, 2d, and a first and a second driving circuit 24s, 24d. Each branch 2s, 2d includes a charging transistor 3s, resp. 3d, a charge-transfer node 4s, resp. 4d, and a boosting capacitor 12s, resp. 12d. Each driving circuit 24s, resp. 24d, comprises a first driving transistor 21s, resp. 21d, a second driving transistor 22s, resp. 22d, a third driving transistor 27s, resp. 27d, a first driving capacitor 23s, resp. 23d, a second driving capacitor 25s, resp. 25d, and a third driving capacitor 26s, resp. 26d. The transistors are all of NMOS type.
In detail, the first driving transistor 21s, resp. 21d, has its drain terminal connected to the drain terminal of the charging transistor 3s, resp. 3d, its gate terminal connected to the intermediate node 5s, resp. 5d, and its source terminal connected to a first terminal of the first driving capacitor 23s, resp. 23d, as well as to the gate terminal of the charging transistor 3s, resp. 3d. The second terminal of the first driving capacitor 23s, resp. 23d, receives a first phase signal A2 and, respectively, a second phase signal B2. The boosting capacitor 12s, resp. 12d, has a first terminal connected to the intermediate node 5s, resp. 5d (as for the charge pump of FIG. 1) and a second terminal receiving a third phase signal B1 and, respectively, a fourth phase signal A1.
The second driving transistor 22s, resp. 22d, has its drain terminal connected to the intermediate node 5s, resp. 5d, its gate terminal connected to a source terminal of the third driving transistor 27s, resp. 27d and to a first terminal of the third driving capacitor 26s, resp. 26d, and its source terminal connected to a first terminal of the second driving capacitor 25s, resp. 25d, to the gate terminal of the charge-transfer transistor 4s, resp. 4d, as well as to the gate terminal of the third driving transistor 27s, resp. 27d. A drain terminal of the third driving transistor 27s, resp. 27d, is connected to the intermediate node 5s, resp. 5d. The second terminal of the second driving capacitor 25s, resp. 25d, receives the second phase signal B2 and, respectively, the first phase signal A2. The second terminal of the third driving capacitor 26s, resp. 26d, receives the fourth phase signal A1 and, respectively, the third phase signal B1.
In the charge pump of FIG. 3, as shown by the waveforms of the phase signals A1, A2, B1, B2 of FIG. 4, charging of the boosting capacitor 12s, resp. 12d, and transfer of charge from the boosting capacitor 12s, resp. 12d, to the output node 11 do not take place for the entire respective half-period. For example, in the charge-transfer step of the first branch 2s, initially (instant t0) the boosting capacitor 12s is brought in a xe2x80x9cready-for-transferxe2x80x9d condition by the third phase signal B1 switching to the high state. Then (instant t1), the fourth phase signal A1 switches to low, turning off the second driving transistor 22s and isolating the gate terminal of the charge-transfer transistor 4s from the intermediate node 5s. Only subsequently (instant t2), the second phase signal B2 switches to high, turning on completely the charge-transfer transistor 4s and enabling connection of the boosting capacitor 12s to the output node 11. Next, as soon as the second phase signal B2 switches again to low (instant t3) transfer of charge by the first branch 2b terminates.
Also transfer of charge from the boosting capacitor 12d of the second branch 2d to the output node 11 does not take place immediately thereafter. In fact, switching to high of the fourth phase signal A1, which brings the boosting capacitor 12d in the xe2x80x9cready-for-transferxe2x80x9d condition, occurs with a delay with respect to switching to low of the second phase signal B2 (instant t4) and, with a succession of steps that is similar to the one described above, connection of the boosting capacitor 12d of the second branch 2d to the output node 11 takes place only subsequently (instant t5). In practice, the time interval t0-t2 represents the dead time between start of the charge-transfer half-period and start of charge transfer proper. The time interval t3-t4 represents the dead time between end of charge transfer and start of the charging step. Altogether, the output 11 sees a dead time wherein neither the branch 2s nor the branch 2d transfers any charge outwards, and which corresponds to the time interval t3-t5.
The four-phase charge pump 28 is therefore far from efficient, in particular in the case of a high oscillation frequency, wherein the precharging time becomes comparable with the effective pumping time. Furthermore, it is complex and requires a large area for accommodating the circuits for generating the four-phase signals.
An embodiment of the present invention provides a charge pump that is free from the drawbacks described above.
According to the present invention there is provided a power charge pump, operating as follows:
Voltage applied to gate terminals of charging transistors and charge-transfer transistors of two parallel pumping branches forming the charge pump is a boosted voltage generated internally and supplied in a crosswise manner. In particular, for driving the charge pump, first and second driving signals are generated respectively for the first and for the second pumping branch via a first and respectively a second driving circuit; the first and second driving signals are also supplied respectively to a first and to a second auxiliary charge pump to obtain respectively first and second voltage-boosted signals; and the first and second boosted voltages are respectively supplied to the second and to the first driving circuit.
According to an aspect of the invention, the voltage applied to the gate terminals of the charging transistors and of the charge-transfer transistors is a boosted voltage generated internally and supplied in a crosswise manner.
According to another aspect of the invention, in a charge pump comprising a first pumping branch and a second pumping branch, which are connected in parallel between a supply node and an output node, the following steps are performed: generating first driving signals and second driving signals respectively for the first pumping branch and for the second pumping branch through a first driving circuit and a second driving circuit, respectively; providing a first auxiliary charge pump and a second auxiliary charge pump; supplying the first driving signals and the second driving signals respectively to the first auxiliary charge pump and to the second auxiliary charge pump to obtain first voltage-boosted signals and second voltage-boosted signals, respectively; and supplying the first voltage-boosted signals and the second voltage-boosted signals to the second driving circuit and to the first driving circuit, respectively.